Increasing bandwidth requirements is becoming hard to meet because of electrical signal attenuation and crosstalk through radiated electromagnetic energy while equalization, coding, and shielding techniques developed to preserve the quality of metal connections may require considerable power and complexity while showing poor scalability.
Optical communications is considered an alternative to copper links as well as for intra-board chip-to-chip communications and high performance data processing (re: “Silicon Photonics for Next Generation System Integration Platform”, Yasuhiko Arakawa, Takahiro Nakamura, Yutaka Urino and Tomoyuki Fujita, IEEE Communications Magazine, March 2013).
EP 2639978-A1 discloses a method and a system of data communications for an electro-optical board for data processing and communications based on the use of a silicon photonic interposer between a support PCB and a plurality of electronic chips mounted onto the optical interposer. This is with ordinary techniques using a hybrid integration of photonics and electronics by face-to-face bonding (flip-chip assembly). An array of optical I/O fibers is connected to waveguides defined in the silicon interposer. Through silicon vias (TSV) created in the photonic interposer provide the electrical path to/from the PCB substrate and the optoelectronic devices inside the silicon photonics die. The optical transmission is inside the silicon photonics die. Although somewhat of a higher parasitic phenomena may generally need to be accounted for at photonic and electronic device interfaces (e.g., Cu pillars and Pi pads), a great technological relief of separating photonics and electronics processes is achieved through such a hybrid integration approach.
The article “A Multi-wavelength 3D-compatible Silicon Photonics platform on 300 mm SOI wafers for 25 Gb/s Applications”, F. Boeuf et al., IEDM13, pages 353-356, reports developments of hybrid integration of silicon photonics. In particular, a 3D assembly of a photonic IC bottom die (PIC) is based on an SOI substrate with an optimized buried oxide (BOX) thickness for insertion loss minimization of grating couplers used to couple light in and out of optical I/O fibers, and companion electronics top die or dies (EIC). This may avoid the technological complications of full monolithic integration (interactions at processing level) and attendant limitation of access by system designers to state-of-the-art CMOS and BiCMOS technologies.
However, even such a hybrid architecture may fall short of efficiently resolving important technical problems in many situations because of several drawbacks and limitations. In particular, the number of usable electronic dies (ICs) may be limited by the maximum area of a single silicon photonic chip that depends on the overall dimensions of a CMOS mask (commonly about 800 mm2). Large size, thin silicon photonic interposers with dense populations of through silicon vias defined therethrough are delicate to handle and assemble onto a PCB. Heat dissipation requirements of the electronic dies (ICs) limit proximity to optics and are often too high to host the electronic dies close to a laser diode array chip. Optoelectronic components integrated in silicon photonic dies may suffer from high sensitivity to large temperature variations, and thermal management may impose complex control circuitry and expensive packaging arrangements. The presence of large ICs bonded onto the silicon photonic interposer may limit optical interconnectivity underneath them.